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Next Generation High Speed Board-Level Interconnect Using Fixed-Load Drivers: CS Department

Next Generation High Speed Board-Level Interconnect Using Fixed-Load Drivers: CS Department

August 05, 2022

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2022 (14)

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Optoelectronic Multi-Chip Module Demonstration System Using Fiber Image Guide Interconnections: CS Department
Next Generation High Speed Board-Level Interconnect Using Fixed-Load Drivers: CS Department
Area, Power, and Pin Efficient Bus Transceiver Using Multi-Bit-Differential Signaling: ISCAS2005
Aggressive Network Interface And Router Designs For Special Purpose Scalable Distributed Processing Systems (Student Shaun Gause), USC Discovery Day 2007
A Cluster-On-A-Chip Architecture For High Throughput Phylogeny Search (SEAGEP09)
Power Efficient, Scalable Hybrid DSP+ARM+FPGA Platform for Computer Vision Tasks, Supercomputing 2013, Nov. 2013

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