A model of a DC power system in development for digital twins for naval shipboard power systems is presented. The model evaluates six load profiles with four model configurations with the goal of removing lumped generation assumptions and adding predictive generation. Results are used to evaluate the relative performance of the configurations compared to initial expectations. Improvements to the model are introduced as well as a basic optimization function to be used in future iterations.

This paper presents threshold voltage instability of commercially available 1.2 kV SiC power MOSFETs from multiple vendors. Time-dependent bias-stress measurements are implemented to define the threshold voltage change incurred by near interface oxide traps. Bias-stress on the gate gives rise to injection of carriers into the gate oxide by direct tunneling to the near interface traps. Positive gate bias tends to increase threshold, whereas, negative gate bias tends to decrease threshold voltage. Threshold voltage shifts for various vendors vary from 0.15 V to 0.74 V under bias-stress of +30 V, and -0.05 V to -0.2 V under bias-stress of -10 V for 50 hours. This wide variation in the shifts between vendors indicates the different trap distribution in their oxides. In general, a positive threshold voltage shift decreases current drive, while a negative shift can cause the device to move into an ON state. However, the shift by itself does not represent an operational problem in power electronics but signifies the high density of defects in the gate oxide which may have significance for useful lifetime of gate oxides.

Breaking through the current power density, efficiency, and cost ceilings is no small feat. With converter designs that reach well beyond 20 kW/L and >99% efficiency, it is no wonder that design optimization has filtered into power electronics to further push these envelopes.

This work examines the gate oxide ruggedness and underlying failure mechanisms of commercially available large-area 1.2 kV 4H-SiC power MOSFETs from multiple vendors. Both gate leakage current and time-dependent dielectric breakdown (TDDB) measurements are performed at various voltage stresses with temperatures between 28°C and 175°C. While some vendors show promising gate oxide reliability results such as low gate leakage current ( 100pA) and >106 hours lifetime at 175°C with VG=20 V, anomalous gate leakage current behaviors and TDDB characteristics are observed for other vendors. The anomalous gate oxide reliability measurement results are related to the pre-existing gate oxide defects and interface traps. Gate leakage current measurements at different temperatures reveal insights into the oxide quality. The authors also observe that constant-voltage TDDB measurement can greatly overestimate the oxide lifetime when a significant amount of extrinsic oxide defects exist before the measurements.

This paper proposes a novel two-level single-stage direct ac-ac converter for realizing a 7.2-kV medium-voltage (MV) solid-state transformer (SST) based on 15-kV SiC mosfets. A new current-fed series resonant converter (CFSRC) topology is proposed to address major challenges in MV ac-ac converters such as achieving zero-voltage switching (ZVS) for the MV mosfets across wide voltage and load ranges and minimizing system capacitance. The topology is analyzed with both time-domain analysis and first harmonic approximation to provide useful equations for circuit design. Constant deadtime strategy is adopted, allowing partial ZVS to occur at low-voltage (LV) levels. ZVS behavior over wide voltage range is investigated, and calculation of the associated loss from partial ZVS is presented. System parameters are optimized based on the tradeoff between conduction loss and switching loss. The 15-kV mosfet has been tested continuously at a park voltage of 10 kV and 37 kHz, indicating stable device operation and an extremely high voltage × frequency figure of merit. Moreover, inherent cycle-by-cycle current limiting in the proposed CFSRC under output short-circuit circumstance is realized by paralleling diodes to the LV resonant capacitors. Without employing any additional current sensors, the input and circulating currents are limited to a safe range automatically when the short-circuit occurs. This paper presents detailed short-circuit protection operating principles and peak resonant current equation to aid the design of the resonant tank. A full-scale and compact SST that converts 7.2 kV ac to 240 V ac is developed to verify the theoretical analysis. This is the highest reported voltage rating for two-level-based power converters without device series connection. ZVS is verified and achieved over wide voltage and load ranges with a peak efficiency of 97.8%. A short-circuit experiment is conducted at 3-kV peak voltage to verify the analysis. Experimental results closely match the theoretical analysis.

A method to design and optimize a Medium Frequency Transformer (MFT) based on commercially available components and semiconductor and converter constraints is presented. The optimization algorithm is used to redesign the transformer for a scaled-down electric vehicle (EV) fast charger using a three-level resonant circuit topology. The main consideration of this paper is the uncertainty caused by modeling assumptions in optimization algorithms. To reduce this uncertainty, space mapping is used to create an optimized design point. Finally, a comparison of the designs found using the original optimization algorithm and the space mapping technique are compared and analyzed. For simplicity, only a single objective optimization routine is employed.

This paper presents a medium-voltage (MV) (12.47 kV), 350 kW electric vehicle (EV) fast charger using 10 kV SiC MOSFETs. Detailed system design procedure based on the 10 kV SiC MOSFET characterization is presented to provide a guide on the 10 kV SiC MOSFET converter development. Taking the advantage of the 10 kV SiC MOSFET s high voltage blocking capability and efficient switching performance, a single module high power density system is designed with the DC/DC stage operates at 25 kHz and the simulated system efficiency exceeds 98%, input current THD lower than 2%. With all the passive components selected, the designed system power density is 1.6 kW/L.

Gate leakage current and constant-voltage time-dependent dielectric breakdown (TDDB) measurements at room temperature and elevated temperatures of commercially available large-area 1.2 kV 4H-SiC power MOSFETs are performed to investigate their gate oxide reliability and better understand their failure modes. It is shown that Fowler-Nordheim (F-N) tunneling current is the dominant mechanism contributing to the gate leakage current. Despite anomalous gate leakage current behaviors that could be caused by interface states densities ( Dit)and near interface oxide traps, leakage currents at normal operating condition ( VG=20 V at 28°C) are less than 100 pA for all vendors. Extrapolation from TDDB measurements shows that the predicted lifetimes when VG=20V at both 28°C and 175°C are far longer than the targeted 10 years.

Designing system-level converters can be complicated. The interweaved intricacies of modular converters to achieve higher voltages while maintaining stable controls and magnetics design must be considered. While there are many difficulties to overcome, the magnetics tend to be the most uncomfortable for power electronics engineers to define in the converter design process due to the lack of direct transition from design and simulation to final hardware outcomes.

Stacking faults in the drift layer of 1.7 kV 4H-SiC MOSFETs result in body diode degradation, poor carrier conduction in on-state, and high leakage current in off-state. In this paper, the results of forward-bias stress on body diodes are analyzed in commercially available 1.7 kV 4H-SiC MOSFETs. Some devices show a significant degradation after forward-bias stress on the internal body diode. This implies that there are significant number of Basal Plane Dislocations (BPDs) present in these devices. These BPDs may be originally present in the drift layer or they may be induced by processing such as room temperature ion-implantation.