In-network Computing with SmartNICs for HPC Applications

Overview

Data Processing Units (DPUs) are programmable processors designed to offload and accelerate infrastructure workloads and data processing. This tutorial introduces the NVIDIA BlueField-3 DPU and examines its programming models including the DOCA SDK, P4, and DPDK. It also demonstrates High-performance Computing (HPC) workloads that can be offloaded to the DPU.

Audience

This tutorial is intended for HPC users, application developers, researchers and developers of programming models and communication libraries, as well as tool developers who are interested in leveraging next-generation SmartNICs for HPC.

Tutorial Goals

By participating in this comprehensive tutorial, attendees will gain:

• An understanding of asynchronous programmable engines, such as SmartNICs, and their evolution in HPC architectures, including an overview of current efforts by major vendors such as NVIDIA, Intel, and AMD.
• Familiarity with programming models for SmartNICs, such as vendor-supported frameworks like P4 and DOCA, OpenMP offloading, and communication offloading with MPI.
• Practical knowledge of leveraging SmartNICs for in-line packet processing, communication offload optimizations, storage optimizations, and algorithmic changes in applications.
• Real-world application experiences and mini-apps case studies that leverage SmartNICs and DPUs
• Hands-on experience with exercises covering a variety of application examples, including tutorials on P4 and DOCA features, blocking and nonblocking MPI collective offload operations, OpenMP offload for DPUs, and using accelerators like Data Path Accelerators (DPAs).